Uses a set of registers to divide the clock, and then some combinational logic to convert from binary to decimal for the display.
Puts a slower square wave output on output 7.
After reset, the counter should increase by one every second.
| # | Input | Output |
|---|---|---|
| 0 | clock | segment a |
| 1 | reset | segment b |
| 2 | segment c | |
| 3 | segment d | |
| 4 | segment e | |
| 5 | segment f | |
| 6 | segment g | |
| 7 | slow clock output |