91 Simple adder used for educational purposes

91 : Simple adder used for educational purposes

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  • Author: Francisco Brito Filho
  • Description: Simple adder used for educational purposes described in VHDL and ported to verilog using ghdl plugin.
  • GitHub repository
  • Clock: 0 Hz

How it works

The adder was adapted from its 8-bit version. See https://github.com/britovski/adder

How to test

See the testbenchs on the previous github repo.

IO

#InputOutput
0i0[3]s[3]
1i0[2]s[2]
2i0[1]s[1]
3i0[0]s[0]
4i1[3]co
5i1[2]
6i1[1]
7i1[0]