212 Generador de PWM

The project is a simple Pulse Width Modulation (PWM) generator with a variable duty cycle. The duty cycle is controlled 
using two buttons: one to increase and another to decrease the duty cycle. The project is designed to operate with a 10 
MHz clock as its time base.

increase_duty and decrease_duty are signals directly connected to ui_in[0] and ui_in[1], respectively.

The code includes debounce logic for the buttons. It uses a counter (counter_debounce) to generate a slow clock enable signal 
(slow_clk_enable). This slow clock is used to sample the button states and eliminate debounce.

The code utilizes a 4-bit counter (counter_PWM) to generate a PWM signal. The duty cycle of the PWM signal is controlled by the 
DUTY_CYCLE variable, which can be increased or decreased using the debounce logic signals (duty_inc and duty_dec).

This is a simple D flip-flop used for debounce. It samples the D input when the en (enable) signal is high.

Connect two buttons to the system. These buttons are used to control the duty cycle of the PWM signal.

Connect an oscilloscope to output pin 0 of the dedicated outputs of the system. Adjust the oscilloscope settings to 
measure and display the PWM signal correctly.