This is a proof-of-concept design to sketch out the TT_UM digital interface for a later project design that will attempt to incorporate both analogue and digital aspects of the basic skeleton shown in this project.
The design is based on the classic circa 1988 model design used in Amateur Radio Packet systems by G3RUH. The initial specification is looking to achieve data rates of between 4800 and 64000 baud, but the design maybe able to service audio 1200 baud packet radio as well.
The design is 1-data-bit per symbol.
The original TNC (Terminal Node Controller) was a Z80 CPU and 8530 Serial Communications Controller. So inline with this I expect to provide an 8-bit CPU (as a future TT project) as a companion to this so the two items taken together should be able to form a complete communications solution of a capable TNC. This is an area I spent a significant amount of my teenage youth understanding and experimenting with that gave me a good grounding in all the digital electonic, radio and computer/CPU theory/practice that is still in use today.
The original PCB board design used:
Due to the need to perform ROM lookups, this is operating in 4 phases sharing 6-bit output from module, and 4-bit input to module. The 4 phases cover a sequence of:
I also need to validate the DAC 8bit loading scheme prevents any chirping (visibily to DAC of partially loaded data, due to multiplex timing differences) of the data because it is loaded in 2 halves.
The master clock (CLK pin) due all the above, it is ncessary to run the clock pin at x4 the x16 of the original design.
| data rate baud | master clock (CLK) | tx clock | tx sample clock |
|---|---|---|---|
| 4,800 | 307,200 | 76,800 | 19,200 |
| 9,600 | 614,400 | 153,600 | 38,400 |
| 19,200 | 1,228,800 | 307,200 | 76,800 |
| 38,400 | 2,457,600 | 614,400 | 153,600 |
| 64,000 | 4,096,000 | 1,024,000 | 256,000 |
| 76,800 | 4,915,200 | 1,228,800 | 307,200 |
Table is in Hz or Baud
The master clock (pin CLK) is driven at x64 the synchrnous data rate. The tx clock rate is derrived from this 'CLK divide-by-4'
The UART clocking is also derived from CLK, and each side (uart RX and uart tx) can be individually configured to be 1:1 or 2:1 the synchronous data rate:
As you can see maybe there is some headroom for faster transmission speeds within a TT project, before needing to increase DAC resolution and explore 4FSK/6FSK/QAM etc...
There are 3 main functional areas with the design:
The type of FSK modem is 2FSK (dual tone) outputting continious wave.
This incorpotates a full-duplex HDLC frame processor attached to a UART (ttl interface), the UART process encodes the frame in format similar to KISS format used by TNCs, with a few modifications.
This manages the receiver clock recovery PLL circuit and interface, the original designs used EPROM lookup tables with 12bit address (which has visibility on at least the previous encoded bit) and provides an 8bit data output.
The data outputs are then fed into a respective 8bit DAC
The receiver has a PLL lock detector which is used to provide DCD (Data Carrier Detect) signal. While the hardware design is capable of full-duplex operation it is often used in Amateur Radio situations in a half-duplex situation with a carrier sense channel sharing algorithym.
The parts that are missing from the design:
It is hoped all items can be incorporated into the same design using the analogue GDS facility with TT and connected to the respective lower digital signal.
At this time we bring out the interconnection points (between analogue and lower digital) to the external interface of TT and we provide a configuration mechnism to be externally or internally driven/internally sourced. This should allow for a significant level of simulation and experimentation by users of the project to understand and explore FSK/PLL theory by picking a testing configuration combintation, being full-duplex it should be able to loop-back at various levels to understand each part better. While also providing those with a Ham Radio license to try out on air communicating with their local users or AMSAT.
Have fun... 73s de G7LED
When the final design is completed, there should be a number of visible and testable aspects available to observe the working of various functions.
I am not expecting this PoV project to yeild good result due to the limited time spent on it just before submission deadlines for TT06.
Check back with the repo for a testing regime.
At this PoC stage, testing with RP2040 and FPGA external boards to validate the electrical interface acrhetecture makes sense and provided the most options.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Rx Data | UART TX | Rx Clock (bidi) |
| 1 | Rx Clock | UART CTS | Up/Down (bidi) |
| 2 | UART RTS | UART DCD | TableAddr[0] |
| 3 | TableData[0] | Rx Error | TableAddr[1] |
| 4 | TableData[1] | Tx Error | TableAddr[2] |
| 5 | TableData[2] | Sending | TableAddr[3] |
| 6 | TableData[3] | TableAddr[4] | |
| 7 | UART RX | Tx Clock Stobe | TableAddr[5] |